The present invention relates to a video memory control apparatus for use with a display in which characters, graphics, and the like are displayed on a picture screen, and in particular, to a video memory control apparatus in which signals of characters or graphics generated by a personal computer or the like and television signals are changed over and then are outputted to a display, thereby effecting a so-called superimpose function to superimpose characters or graphics on a television picture reproduced on a picture screen of a display.
To display a superimposed picture of a character or graphics on an image of television signals, an appropriate synchronization is required to be established between the television signals and the character or graphics signals.
However, if a phase shift occurs in the synchronization signal of the television signals and that of the character or graphics signals, the synchronization of the picture displayed on the display is disturbed and hence the image of the picture screen is distorted or the data stored in the video memory is destroyed in some cases.
Such a conventional video memory control circuit is described in the Japanese Patent Examined Publication No. 57-41154. According to this video memory control circuit, in order to prevent the adverse effect due to the phase shift of the synchronization signals, when a phase shift takes place in the horizontal synchronization signal of the television video signal, the clock count operation is kept achieved for a predetermined count during the horizontal period in which the phase shift occurs and thereafter the count operation is stopped; and then the clock count operation is restarted with the next horizontal synchronization signal.
However, in the conventional video memory control circuit described above, the period for which the clock count operation is stopped after the predetermined count of the count operation due to the phase shift of the horizontal synchronization signal becomes to be up to a maximum of a horizontal period. This clock count stop period causes a disadvantage that accesses for effecting the write and read operations of display data on the video memory is prevented. The operation to write display data in the video memory is ordinarily controlled by a microprocessor (to be abbreviated as MPU); however, during the clock count stop period, the MPU is prevented from accessing the video memory and hence the processing efficiency of the MPU is lowered.
Particularly, in a system in which a memory divided into a plurality of storage areas and each storage area is allocated to the display, the system work memory, the buffer memory, or the like, when the clock count operation is stopped, the read and write operations are inhibited not only on the display area but also on the other areas, which deteriorates the processing speed of the system as a whole.
There has been a video memory control apparatus effecting a so-called cycle steal display read in which the operation clock of the MPU is commonly used for the count output signal of the display circuit and an unused period of the display read cycle is utilized by the MPU to access the video memory. In an apparatus achieving the cycle steal display read, the MPU clock is stopped for the clock count stop period of the display circuit, which leads to the disadvantages that the processing of the MPU is stopped for a maximum of a horizontal period and that a runaway of the MPU occurs due to a sudden stop of the MPU clock.